This invention relates generally to clock distribution in integrated circuits and specifically to a clock distribution scheme using a delay lock loop in a programmable logic circuit.
As the level of integration in semiconductor integrated circuits (ICs) increases, signal delays due to parasitic resistance-capacitance loading become larger. This is especially true of high fan-out global signal lines such as synchronous clocks. Clock signals in modern programmable logic devices may drive several thousand registers. This is a considerable load to the clock driver. Clock tree structures can be implemented on-chip to minimize clock skew among registers. However, the base trunk clock driver must be capable of driving this clock tree structure and, as a result, a buffer delay of several nanoseconds is typically incurred.
One approach to clock distribution uses a phase locked loop (PLL). This approach uses a phase locked loop to synchronize a clock distribution signal to a reference clock signal. Since the phase locked loop generates an internal clock signal and synchronizes it to the reference clock signal from an external source, the reference clock signal does not drive the clock tree structure.
However, some problems exist with implementing a PLL in a typical integrated circuit since the PLL uses analog devices such as a phase frequency detector (PFD), charge pump and low pass filter. These problems include, among others, poor stability and performance in a noisy environment.
It is desirable to use a circuit which achieves clock distribution while minimizing the number of components, thus reducing the area on the chip used by the clock distribution circuit.